High-performance power electronic devices continue to make great strides in voltage, current and power levels. But the higher performance comes with higher power dissipation levels that place a strain on electrical interconnections, on cooling and on mechanical integrity. Conventional approaches to packaging power electronics uses discrete packaged devices mounted onto a board or substrate or a hybrid module in which bare chips are mounted onto a substrate and connected to the substrate by wire bonds have significant performance limitations. The discrete packages can be plastic molded, metal sealed cans or sealed ceramic carriers, containing one power chip wire bonded to a plastic package lead frame. The bare power chip is solder attached to a pad on the substrate and the thermal path is through these interfaces, through the substrate, through an adhesive or thermal grease into a cooling structure. The number of thermal interfaces and the poor thermal conductance of the substrates and the interface materials causes excessively high junction-to-ambient thermal resistances, limiting device operation and increasing the junction temperature beyond limits. These thermal effects can also cause designers to move devices apart to increase thermal spreading, at the expense of a larger module size, increased electrical parasitics and a more costly assembly.
Power semiconductor chips such as power JFETs, MOSFETs, IGBTs and diodes are devices for controlling large currents, and they produce large amounts of heat. Consequently, when these semiconductor chips are built into packages, it is arranged to achieve a sufficient cooling performance (heat radiation). In a conventional power module technology, consisting of a plurality of semiconductor chips built into a package, an insulating substrate made of a high thermal conductivity ceramic is used, and the plurality of semiconductor chips are mounted on this insulating substrate, and main electrodes provided on the lower principal surfaces of the semiconductor chips are connected by soft soldering to a copper thick film provided on the insulating substrate. Main electrodes and control electrodes provided on the upper surfaces of the IGBT chips are connected to a copper thick film provided on the insulating substrate by wire bonding. The insulating substrate is soldered to a heat radiation base plate made of copper. By this means, heat produced by the semiconductor chips is radiated through the insulating substrate disposed on the lower surface side of the semiconductor chips. In this conventional technology, heat is only radiated from one surface of each of the semiconductor chips, there is a limit to how much the heat-radiation performance can be raised, and reducing the size of the construction of the power module.
An advanced packaging technology that addresses the thermal and mechanical performance requirements while providing a high electrical performance interconnect structure are required in the future for power electronics targeted at application areas such as military, aerospace, medical and industrial electronics. These application areas all are moving to semiconductors with higher voltage, higher current, higher power dissipation and faster switching speeds, and the devices are outstripping the electrical, mechanical and thermal capabilities of traditional packaging approaches. The advanced packaging technology should replace the wire-bonded die on low-performance ceramic substrates with one side cooling path with a direct double side cooled metal-based interconnect structure. One example of this construction is an electrically isolated and thermally conductive double side pre-packed component, which is disclosed in, for example, U.S. patent application publication No. 2003/0132511. In this pre-packed component, stamped lead members, contact electrodes, semiconductor chips and the like are positioned between a pair of ceramic substrate members. Another example of this construction is a high reliability copper graphite conductor substrate power device package, which is disclosed in, for example, IEEE 44th Annual International Reliability Physics Symposium, San Jose, 2006, page 613. This package has a structure wherein an IGBT and diode chips are sandwiched by two copper graphite conductor substrates, gold bumps and solder bumps for planarization and interconnection, and a second copper graphite layer for topside interconnect and double sided heat removal. However, without the inherent stress relief of wire bonds, double-sided construction requires very careful material selection to eliminate expansion mismatch at the interfaces, while providing high conductivity for both electrical and thermal conduction. The reduced Coefficient of thermal expansion of the heat transfer layer not only provides for a reliable interface, but due to the reduced stress on the electrical insulator layer allows the use of very thin AlN dielectric to further improve the heat transfer. In this configuration, to obtain electrical connection between the electrodes of the IGBT and diode chips and the electrodes, the semiconductor chips are sandwiched by two copper graphite conductor substrates, gold bumps and solder bumps for planarization. However, on the upper side of the semiconductor chip, because the electrodes on this upper side and electrodes provided on the upper insulating substrate are connected by metal bumps, the area of the connection is small. Consequently, there has been the problem that the electrical resistance is large, which is disadvantageous to obtaining large currents, and that heat produced by the semiconductor chip is not readily transmitted to the insulating substrate, and thus the heat-radiation performance is poor. Also, this package design requires external connection buses bonding together with the semiconductor chips bonding. In this asymmetric design layout, it difficult to control to achieve a uniform stress distribution in the package after the full assembly process, which may leads to large stresses on the semiconductor chips. The semiconductor chips like IGBTs and MOSFETs having MOS gate structures have the characteristic that they are vulnerable to stresses.